1. Field of the Invention
This invention relates generally to storage elements and in particular to preventing violations of the setup time requirement of flip-flops.
2. Description of Related Art
Storage elements, such as latches and flip-flops, are ubiquitous in complex digital circuits. The D-type flip-flop is perhaps the most popular type of storage element. FIG. 1(a) shows the logic diagram of D-type flip-flop 100 having data input terminal D, clock input terminal CLK, data output terminal Q, and inverted data output terminal |Q. Many embodiments of D-type flip-flops, for example CMOS implementations, also have an inverted clock input terminal |CLK (not shown) which receives an inverted clock input signal |CLK. Furthermore, some embodiments of D-type flip-flops do not provide inverted data output terminal |Q. To avoid confusion, signals on the various terminals are given the same names as the terminals themselves, whenever possible. Typically, for D-type flip-flops, rising edges of clock input signal CLK are active edges and falling edges are inactive edges. However, in some circuits falling edges are active edges, and rising edges are inactive edges.
FIG. 1(b) shows the timing diagram of D-type flip-flop 100. On active (rising) edge 110 of clock input signal CLK, D-type flip-flop 100 passes signal V1 on data input terminal D to data output terminal Q, which changes to signal V1 after a time delay T.sub.-- cq (clock-to-out), representing the propagation delay of D-type flip-flop 100. D-type flip-flop 100 ignores changes to data input signal D, such as the transition from signal V1 to signal V2, until active (rising) edge 120 of clock input signal CLK. At active (rising) edge 120, data input terminal D is receiving signal V3. Therefore, after time delay T.sub.-- cq, data output signal Q is also signal V3.
For D-type flip-flop 100 to function properly, data input signal D must satisfy two timing constraints, a setup time and a hold time, with respect to active edges of clock input signal CLK. Setup time T.sub.-- setup is the minimum time that data input signal D must be at the proper signal level before the active clock edge. Hold time T.sub.-- hold is the minimum time that data input signal D must remain at the proper signal level after the active clock edge. If either the setup time or hold time is violated, data output signal Q of D-type flip-flop 100 is undeterminable.
The D-type flip-flop can be implemented using many well known circuits. The exact details of each implementation are dependent upon the process technology and available semiconductor area. The important characteristics of a D-type flip-flop are given by the timing relationships among the signals on data input terminal D, data output terminal Q, and clock input terminal CLK.
FIG. 2 shows a well known static D-type flip-flop 200 constructed with two transmission gates and four inverters. Data input signal D is coupled to the input terminal of transmission gate 210. Transmission gate 210 is coupled to clock input terminal CLK and inverted clock input terminal |CLK so that transmission gate 210 transmit data only when clock input signal CLK is in an inactive state (a logic low). When a transmission gate is transmitting data, the transmission gate is said to be ON. If the transmission gate is not transmitting data, i.e. if clock input signal CLK is at a logic high for transmission gate 210, the transmission gate is said to be OFF. Inverter 220 and inverter 230 are coupled with transmission gate 210 to form a storage element commonly called a D-type latch. Transmission gate 210 is constructed to provide more driving power, i.e. more current sourcing strength when driving a logic high and more current sinking strength when driving a logic low, than inverter 230. Thus, transmission gate 210 can overpower the signal from the output terminal of inverter 230 and force a new logic state to the input of inverter 220 when transmission gate 210 is ON. When transmission gate 210 is OFF, inverter 230 provides a feedback path so that the signal level on the input terminal of inverter 220 is maintained by the output terminal of inverter 230. Thus inverter 220 and inverter 230 form a storage element for the value of the signal which was driven by transmission gate 210 before transmission gate 210 is turned OFF.
The output terminal of inverter 220 is coupled to the input terminal of transmission gate 240. Transmission gate 240, inverter 250, and inverter 260 form a second D-type latch. However, transmission gate 240 is coupled to clock input terminal CLK and inverted clock input terminal |CLK so that transmission gate 240 is ON when clock input signal CLK is in the active state (a logic high). The functionality of static D-type flip-flop 200 is explained with reference to the timing diagram of FIG. 1(b). Before active (rising) edge 110, clock input signal CLK is at a logic low. Therefore, transmission gate 210 is ON, but transmission gate 240 is off. Data value V1 on data input signal D is transmitted through transmission gate 210 and stored by inverter 220 and inverter 230. Since transmission gate 240 is OFF, data value V1 does not propagate to data output Q of static D-type flip-flop 200 before active edge 110. After active edge 110, clock input signal CLK is at a logic high. Therefore, transmission gate 210 is OFF, and transmission gate 240 is ON. Since inverter 220 and inverter 230 maintains data value V1 at the input terminal of inverter 220, an inverted version of data value V1 is transmitted through transmission gate 240 to the input terminal of inverter 250. Inverter 250 then drives data value V1 to data output terminal Q of static D-type flip-flop 200.
Since transmission gate 210 is off while clock input signal CLK is at a logic high, static D-type flip-flop 200 ignores the transition of data input signal D from data value V1 to data value V2. After inactive (falling) edge 115, transmission gate 210 is ON so that data value V2 is transmitted to inverter 220. However transmission gate 240 is OFF so that inverter 250 is isolated from inverter 220. Therefore, inverter 250 and 260 maintain data value V1 on data output terminal Q, until active edge 120 of clock input signal CLK.
For static D-type flip-flop 200 to function properly, data input signal D must satisfy the setup and hold time constraints of static D-type flip-flop 200. Referring to FIGS. 1(b) and 2, if an inverted copy of data value V1 is not driven by inverter 220 before active edge 110, inverter 230 drives whatever previous data value was being stored by inverter 220 and inverter 230, onto the input terminal of inverter 220. Therefore, inverter 220 may never properly drive an inverted version of data value V1. Accordingly, data value V1 must be present on data input terminal D before an active edge long enough for inverter 220 to drive an inverted copy of data input signal D on the output terminal of inverter 220. Therefore, the set up time for static D-type flip-flop 200 is the worse case propagation delay of transmission gate 210 plus the worse case propagation delay of inverter 220. Similarly, data input signal D should remain valid long enough after an active edge to insure no spurious signals are driven onto the input terminal of inverter 220 by transmission gate 210. Therefore, the hold time of static D-type flip-flop 200 is the worse case propagation delay of transmission gate 210.
Faster flip-flops can be created by using dynamic circuits. Dynamic circuits have two distinct functional periods: a precharge period and an evaluation period. During the precharge period, typically when clock input signal CLK is low, certain nodes within the dynamic circuit are precharged to specific precharged states. During the evaluation period the input signals to the circuit are evaluated to generate the output signals of the circuit by discharging one or more of the precharged nodes. The primary disadvantage of dynamic circuits is that the output signal of the dynamic circuit is not valid during the precharge period.
FIG. 3 shows a well known dynamic D-type flip-flop 300 constructed with three PMOS transistors and three NMOS transistors. Data input signal D is coupled to the gate terminal of PMOS transistor 310 and the gate terminal of NMOS transistor 330. Clock input signal CLK is coupled to the gate terminal of PMOS transistor 320, the gate terminal of PMOS transistor 340, and the gate terminal of NMOS transistor 360. During a precharge period, PMOS transistor 340 precharges data output terminal Q to a logic high state, regardless of the value of data input signal D or the previous value of data output signal Q.
During an evaluation period, if data input signal D is at a logic high, NMOS transistor 330 is ON to pull the signal on node 325 to a logic low. Since node 325 is coupled to the gate terminal of NMOS transistor 350, NMOS transistor 350 is turned OFF during evaluation periods in which data input signal D is at a logic high. Therefore, data output terminal Q is not discharged and remains at a logic high.
If data input signal D is at a logic low prior to the evaluation period, node 325 is pulled to a logic high by PMOS transistor 320 and PMOS transistor 310. The setup time of dynamic D-type flip-flop 300 is determined by the time necessary to precharge node 325 through PMOS transistor 310 and PMOS transistor 320. Since node 325 is at a logic high at the beginning of the next evaluation period, NMOS transistor 350 is turned ON. Therefore, data output terminal Q is discharged to a logic low through NMOS transistor 350 and NMOS transistor 360 at the beginning of the evaluation period when clock input signal CLK is at a logic high. Although dynamic D-type flip-flop 300 has very good setup time characteristics the inability to of dynamic D-type flip-flop 300 to maintain data output signal Q valid for an entire clock period limits the usefulness of dynamic D-type flip-flop 300.
As the frequency of integrated circuits and electronic systems have increased, the time allowed to generate and propagate a signal to the input terminal of a storage element has decreased. Therefore, satisfying long setup time requirements for storage elements is an obstacle to increasing clock frequency and therefore performance of integrated circuits and electronic systems. Hence, there is a need for a storage element with only minimal setup time requirements which provide valid outputs for an entire clock period, i.e. until after the next active edge of the clock input signal.